Freescale Semiconductor /MKV40F15 /PORTD /PCR0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PCR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PS 0 (0)PE 0 (0)SRE 0 (0)PFE 0 (0)ODE 0 (0)DSE 0 (000)MUX0 (0)LK 0 (0000)IRQC0 (0)ISF

ODE=0, PE=0, SRE=0, DSE=0, PS=0, IRQC=0000, ISF=0, LK=0, MUX=000, PFE=0

Description

Pin Control Register n

Fields

PS

Pull Select

0 (0): Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

1 (1): Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

PE

Pull Enable

0 (0): Internal pullup or pulldown resistor is not enabled on the corresponding pin.

1 (1): Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

SRE

Slew Rate Enable

0 (0): Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

1 (1): Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

PFE

Passive Filter Enable

0 (0): Passive input filter is disabled on the corresponding pin.

1 (1): Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

ODE

Open Drain Enable

0 (0): Open drain output is disabled on the corresponding pin.

1 (1): Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

DSE

Drive Strength Enable

0 (0): Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

1 (1): High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

MUX

Pin Mux Control

0 (000): Pin disabled (analog).

1 (001): Alternative 1 (GPIO).

2 (010): Alternative 2 (chip-specific).

3 (011): Alternative 3 (chip-specific).

4 (100): Alternative 4 (chip-specific).

5 (101): Alternative 5 (chip-specific).

6 (110): Alternative 6 (chip-specific).

7 (111): Alternative 7 (chip-specific).

LK

Lock Register

0 (0): Pin Control Register fields [15:0] are not locked.

1 (1): Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

IRQC

Interrupt Configuration

0 (0000): Interrupt/DMA request disabled.

1 (0001): DMA request on rising edge.

2 (0010): DMA request on falling edge.

3 (0011): DMA request on either edge.

8 (1000): Interrupt when logic 0.

9 (1001): Interrupt on rising-edge.

10 (1010): Interrupt on falling-edge.

11 (1011): Interrupt on either edge.

12 (1100): Interrupt when logic 1.

ISF

Interrupt Status Flag

0 (0): Configured interrupt is not detected.

1 (1): Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

Links

() ()